Area consumption is an important design consideration in many semiconductor applications. In applications such as mobile phones and RF applications, reducing the necessary circuit board footprint for the electronic subcomponents (e.g., amplifiers, processors, receivers, etc.) is highly desired. For this reason, some package designs employ stacking techniques wherein multiple semiconductor dies (chips) or multiple semiconductor packages are stacked on top of one another. In the case of chip-on-chip stacking technology, two semiconductor dies are attached to one another in a stacked arrangement with bond wire connections to the dies. The stacked chip arrangement with wire bond connections is then molded to form the final package.
In some applications it is desirable to stack two different size chips on top of one other. Conventionally, the smaller chip is stacked on top of the larger chip. This configuration allows for the terminals of the larger chip to be electrically accessible at the peripheral uncovered region of the chip. However, this chip arrangement is not well suited for applications in which the smaller chip generates more heat during operation than the larger chip. In that case, it is preferable to place the smaller chip at the bottom of the package so that it can come into close or direct contact with an external heat sink.
To date, packaging solutions for stacking a larger chip on top of a smaller chip have various drawbacks. Conventional designs employ relatively long and complex bond wire connections which have high parasitic values and/or utilize intermediate redistribution layers which add cost and complexity to the design.